Modern semiconductor devices are built on semi-conducting substrates such as silicon substrates that have P.sup.+ and N.sup.+ type doped regions in the substrates as basic elements of the device. These doped regions must be connected in a specific configuration to form a desired circuit. The circuit needs to be accessible to the outside world through conducting pads for testing and through bonding into a packaged chip. To form a semiconductor circuit, at least one layer of a conducting material such as metal must be deposited and patterned to form contacts and interconnects between the different regions of the chip. For instance, in a typical semiconductor fabrication process, a silicon wafer is first covered with an insulating layer and then, patterned and etched for contact openings in the insulating layer. A conductive material is then deposited and defined to form contact plugs and interconnecting leads.
Contact windows (or holes) to a silicon or silicide layer are usually defined and etched in an insulating layer, i.e., a dielectric material layer, by using lithographic and dry etching techniques. A dry etching technique works anisotropicallly to enable the opening of contact holes that have high aspect ratios. Once formed, contact holes can be filled with a conducting material such as a metal to form vertical connections to a first level metal. Contact holes can also be made by a wet etch process. A wet etch process is carried out by immersing a wafer in an appropriate etchant solution or by spraying the wafer with a solution. When a wet etch process is used, the etching action is isotropic in nature such that the material is etched in both the lateral and the vertical directions. Lateral etching in a wet etch process produces undercutting under a mask which is undesirable in most fabrication processes. On the other hand, a dry etch process etches anisotropically and creates vertical sidewalls in a contact hole such that the top and the bottom of the hole have almost the same dimensions. The dry etch process is frequently used in modern sub-micron devices since it does not create undercutting problem and does not require or waste additional lateral area for a contact hole. The dry etching process further provides the benefits of reduced chemical hazard and waste treatment problems, easily achievable process automation and tool clustering. Two of the most widely used dry etching techniques are the plasma etching technique and the reactive ion etching technique.
While dry etching technique provides significant improvement in dimensional control and therefore is popular in VLSI and ULSI fabrication methods, it also has some limitations. One of such limitations is its inability of scaling down patterning dimensions. In a modern ULSI device, both the horizontal and the vertical device dimensions must shrink continuously to accommodate the ever increasing density of the device. The ability of a fabrication technique to scale down devices to smaller geometries therefore becomes increasingly important. The minimum feature size, i.e., the size of a contact hole, the smallest line-width or line-to-line separation which can be printed on the surface of a chip controls the number of circuits that can be placed on the chip and therefore has a direct impact on the chip density. The evolution of high density chip design is therefore limited by the evolution of lithographic techniques which are normally used to lay down device geometries on a chip.
Among the major lithographic techniques, optical, electron-beam, X-ray and ion-beam, optical lithographic technique using an ultraviolet (UV) light source has been the most important technology. The most commonly used ultraviolet light source for optical lithography are high-pressure arc lamps and laser sources. Major regions of the emitted light spectrum that are produced include the deep ultraviolet (DUV) region which is in the 100.about.300 nm range, the mid-UV region which is in the 300.about.360 nm range, and the near-UV region which is in the 360.about.450 nm range. For instance, when a mercury-xenon arc lamp is used, the dominant wavelengths produced are 254 nm (DUV), 365 nm (I-line), 405 nm (H-line) and 436 nm (G-line). Since most of the photoresist materials require a photo energy higher than 2.5 eV for proper exposure, only wavelengths of 436 nm or shorter can be considered for lithography. When the minimal feature size desired is larger than about 2 .mu.m, the full emitted spectrum of a mercury-xenon arc lamp can be used to expose the resist. For smaller feature sizes, the lens is corrected for one or two of the wavelengths and filters are used to remove the remainder of the spectrum. For instance, the G-line wavelength can be used for feature sizes down to approximately 0.8 .mu.m while the I-line wavelength can be used for feature sizes in the range between 0.4.about.0.8 .mu.m. For even smaller feature sizes, i.e., below 0.4 .mu.m, shorter wavelengths such as the DUV wavelength at 248 nm must be used with very sensitive DUV photoresist.
In modern VLSI manufacturing, state-of-the-art fabrication process for 16 Mbit or larger DRAMs is designed by the less than 0.4 .mu.m process, i.e., a 0.25 .mu.m process. The diameters of contact holes, for example, have to be less than 0.3 .mu.m. Since the I-line capability is only 0.4 .mu.m (with adequate process margin), the shorter wavelength DUV technique and very sensitive DUV photoresist material must be used. The DUV technique and the DUV photoresist material are both high cost and therefore significantly increase the fabrication costs of the IC device.
FIGS. 1 and 2 illustrate a conventional process wherein a photolithographic method and a dry etching technique are used to form contact holes that have vertical sidewalls in a dielectric material layer. The figures illustrate the limitation on the minimum diameter of the contact holes that can be formed due to the resolution limit of the I-line wavelength. In FIG. 1, a semiconductor device 10 is shown which has a semi-conducting substrate 12 and a dielectric film layer 14 deposited on top. The semi-conducting substrate 12 can be a silicon substrate and the dielectric film layer 14 can be a silicon oxide layer or a silicon nitride layer. On top of the dielectric film layer 14, a photoresist layer 16 is first deposited and then patterned to create openings 20. The photoresist layer 16 is patterned by an optical method using ultraviolet I-line wavelength and thus, the resolution is limited to 0.4 .mu.m as shown by A in FIG. 1. After the photoresist layer 16 is exposed and developed, contact holes 22 having a diameter of A are dry etched in the dielectric film layer 14. Since a dry etching technique, i.e., a reactive ion etching technique, is capable of producing openings of vertical sidewalls, the contact holes 22 formed has substantially vertical sidewalls such that the top of the hole and the bottom of the hole have the same diameter of A (or 0.4 .mu.m). When a contact hole smaller than 0.4 .mu.m is desired, the more expensive and difficult photolithographic technique that utilizes deep UV wavelength and very sensitive photoresist material must be used.
It is therefore an object of the present invention to provide a method for forming contact holes of reduced dimensions that is beyond the resolution limit of normal I-line photolithographic technique.
It is another object of the present invention to provide a method of forming cavities in an electronic device of reduced dimensions that does not require the use of expensive deep-UV photolithographic technique and deep-UV photoresist material.
It is a further object of the present invention to provide a method of forming cavities in a semiconductor device of reduced dimensions utilizing the I-line photolithographic technique by making minor modifications in the fabrication process.
It is another further object of the present invention to provide a method of forming cavities in a semiconductor device such as contact holes and line spacings of reduced dimensions by using in-situ formed polymeric sidewall spacers on a photoresist layer.
It is yet another object of the present invention to provide a method of forming contact holes or line spacings of reduced dimensions by utilizing polymeric sidewall spacers formed on a photoresist layer as masks for etching cavities in a non-conducting layer deposited on a semiconductor substrate.
It is still another object of the present invention to provide a method of forming contact holes of reduced dimensions by using polymeric sidewall spacers that are formed by reactant gases substantially similar to those used in the dry etching process for the holes.
It is still another further object of the present invention to provide a method of forming contact holes of reduced dimensions by forming polymeric sidewall spacers on a photoresist layer and etching contact holes in a dielectric layer in the same process chamber.
It is yet another farther object of the present invention to provide a method of forming contact holes of reduced dimensions by forming polymeric sidewall spacers on a photoresist layer by a reactant gas mixture by including C.sub.4 F.sub.8 and CHF.sub.3.